Critical path

Also called: longest path, worst-case path, slowest path

The input-to-output path with the largest total propagation delay. Its delay is the whole circuit's tpd and limits the clock speed.

A circuit has many paths from its inputs to its outputs. Each path's path delay is the sum of the tpd of every gate on it. The critical path is the one with the largest total. Only after that long is every output guaranteed correct, so its delay is the circuit's propagation delay.

Why it matters:

In a clocked design the critical path between two registers sets the minimum clock period, and so the maximum clock frequency of the whole chip.
Speeding up a gate that isn't on the critical path changes nothing.
Speed up the critical path enough and another path becomes the slowest: the critical path moves.

How to find it:

List every path from each input to the output. An input that fans out to several gates has several paths.
Add tpd along each one.
The largest total is the critical path.

It is the path with the most delay, not the most gates. A single slow gate, such as an XOR, can outweigh several fast ones. A classic example is the carry chain of a ripple carry adder. Its opposite is the short path.

Worked examples

Example

Finding the critical path

In the circuit above, F = . The delays are AND 40 ps, OR 50 ps and XOR 90 ps.

1.
A → AND → OR → XOR: 40 + 50 + 90 = 180 ps. B takes the same route: 180 ps.
2.
C → OR → XOR: 50 + 90 = 140 ps.
3.
D → XOR: 90 ps.
4.
The largest total is 180 ps, from A or B. That's the critical path, and the circuit's tpd = 180 ps.

Example

The critical path moves

Same circuit. The AND gate is replaced by one with tpd = 10 ps. What is the circuit's tpd now?

1.
A or B path: 10 + 50 + 90 = 150 ps.
2.
C path: still 140 ps. D path: still 90 ps.
3.
The A/B path is still critical, now at 150 ps.
4.
Make the AND gate instant and the A/B path drops to 140 ps, tying with C. Past that point a faster AND gate can't help: the OR and XOR now set the delay.

Common mistakes

Picking the path with the most gates. Add the delays; one slow gate can outweigh several fast ones.
Forgetting that an input which fans out to several gates has several paths.
Speeding up a gate off the critical path and expecting the circuit to get faster.
Not rechecking after a change. The critical path can move to a different route.

Practice Critical path

Interactive questions with instant feedback and a worked solution for every wrong answer.

Timing and Sequential Logic lesson full course

And 5 more in the Timing and Sequential Logic lesson.

Practice exams

Learn it step by step

Critical path is taught in Timing and Sequential Logic and Adders and ALUs.

Timing and Sequential Logic →Adders and ALUs →

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