Mode select

Also called: mode-select inputs, mode control, mode inputs, S1 S0, operation select

Control inputs that choose which operation a multi-function register performs at the next clock edge, e.g. S1 S0 on a universal shift register.

Mode-select inputs tell a multi-function register which job to do at the next edge. In a universal shift register, two inputs S1 S0 pick one of four modes:

00: hold
01: shift right
10: shift left
11: parallel load

In hardware, the mode inputs are the select lines of the 4:1 multiplexer in front of every flip-flop. Every MUX gets the same S1 S0, so all bits perform the same operation at once.

Two mode bits allow 4 operations; in general k mode bits allow 2ᵏ. A simple load enable register is the one-bit case: L chooses between hold and load.

Like every synchronous input, the mode only matters at the rising edge. It may change freely between edges.

Designing the mode logic: when a register is controlled by higher-level signals ("load when X, otherwise shift when Y"), write S1 and S0 as functions of those signals so that each situation produces the right code.

		S1	S0
0	0	0	0
0	1	0	1
1	0	1	1
1	1	1	1

Worked example

Example

Deriving S1 and S0

A universal shift register (00 hold, 01 right, 10 left, 11 load) must load when X = 1, otherwise shift right when Y = 1, otherwise hold. The table above is the result.

1.
X = 1: load, code 11. So S1 = 1 and S0 = 1.
2.
X = 0, Y = 1: shift right, code 01. S1 = 0, S0 = 1.
3.
X = 0, Y = 0: hold, code 00.
4.
S1 is 1 only when X = 1: S1 = X.
5.
S0 is 1 when X = 1 or Y = 1: S0 = .

Common mistakes

Assuming every part uses the same codes. Some universal registers swap the meaning of 01 and 10.
Thinking the mode stops the clock in hold mode. Hold is just the MUX passing Q back in.