NAND SR latch

Also called: NAND latch, active-low SR latch, cross-coupled NAND latch, SR-bar latch, S-bar R-bar latch

An SR latch built from two cross-coupled NAND gates. Its inputs are active-low: pulling S' to 0 sets Q, pulling R' to 0 resets it.

The NAND SR latch does the same job as the NOR SR latch with two NAND gates. A NAND outputs 1 whenever any input is 0, so here the inputs act when they are 0. They are active-low, written and .

= 1, = 1: hold.
= 0, = 1: set, Q = 1.
= 1, = 0: reset, Q = 0.
= 0, = 0: forbidden. Both outputs are forced to 1.

In the gates, Q = and = .

The four behaviors match the NOR latch with every input level flipped. Invert both NAND inputs and you get the equivalent NOR inputs.

Why it exists: NAND gates are cheap and common, and many real control signals are active-low anyway, so the NAND version is often the natural choice. It is also the core of the preset and clear logic inside many flip-flops, which is why those pins are so often active-low.

A quick way to read one: look for the input sitting at 0. That is the one doing something. If neither is 0, the latch holds.

Worked examples

Example

Tracing a NAND latch

Q starts at 0. Each slot gives the levels on and . Find the input at 0.

1.
Slot 1: both inputs 1, hold. Q = 0.
2.
Slot 2: = 0, set. Q = 1.
3.
Slots 3–4: both 1, hold at 1.
4.
Slot 5: = 0, reset. Q = 0.
5.
Slots 6–7: hold at 0.
6.
Slot 8: = 0, set again. Q = 1, held through slot 10.

Example

Following a set through the gates

The latch holds Q = 0, = 1 with both inputs at 1. Then is pulled to 0 and released. Follow the gate equations.

1.
= 0: the Q gate has a 0 input, so Q = = (0·1)' = 1.
2.
The gate now sees = 1 and Q = 1, so = (1·1)' = 0.
3.
returns to 1. The Q gate sees 1 and = 0, so Q = (1·0)' = 1. It stays set.
4.
Translated to a NOR latch, this was S = 1, R = 0 (a set) followed by S = R = 0 (a hold).

Common mistakes

Using the NOR table on a NAND latch. Both inputs at 0 is forbidden here, and both at 1 is hold.
Thinking the forbidden case gives Q = Q' = 0 as on the NOR latch. On the NAND latch both outputs go to 1.
Reading the bar as "not used". is still the set input; it just acts when it is 0.

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