Asynchronous preset

Also called: preset, PRE, PR, async preset, direct set, asynchronous set

A flip-flop input that forces Q to 1 immediately, without waiting for a clock edge, and overrides the clock and data inputs while asserted.

An asynchronous preset (PRE) is a pin that forces a flip flop's Q to 1 right away. Asynchronous means "not in step with the clock": it does not wait for an edge.

While preset is asserted, Q = 1, whatever the clock, D, J, K or T are doing.
When it is released, the flip-flop goes back to normal and the next active edge loads as usual.

Its partner is the asynchronous clear (CLR), which forces Q to 0. Together they are sometimes called the direct inputs.

Why they exist: at power-up, flip-flops can wake as 0 or 1 at random. Preset and clear put a circuit into a known starting state, even before the clock has started. A ring counter that must start at 1000 is a typical use: preset the first flip-flop, clear the rest.

They are often active-low, drawn with a bubble and labeled or PRE with a bar. Then the pin sits at 1 in normal operation and is pulled to 0 to act. Internally they act directly on the flip-flop's latch, like the inputs of a NAND SR latch.

Never assert preset and clear together. Like S = R = 1 on an sr latch, the result is invalid.

By contrast, D, J, K and T are synchronous inputs: they only matter at the clock edge.

Worked examples

Example

Preset between edges

A positive-edge D flip-flop has D = 0 throughout and an active-high preset PRE. Q starts at 0. PRE pulses high in slot 3, while CLK is low.

1.
Slot 2: rising edge, D = 0. Q stays 0.
2.
Slot 3: PRE = 1. There is no edge, but Q jumps to 1 immediately.
3.
Slot 4: PRE is released and a rising edge arrives with D = 0. Q loads 0.
4.
The preset worked instantly, and the next edge took over again as soon as it was released.

Example

Active-low preset and clear in normal use

A D flip-flop has active-low and pins, both at 1. It has just loaded D = 0, so Q = 0. Then is pulsed low, and later is pulsed low, both between clock edges.

1.
With both pins at 1, neither is asserted, so the flip-flop follows its clock and D normally.
2.
= 0 forces Q = 0. Q was already 0, so nothing visible changes.
3.
= 0 forces Q = 1 at once, with no clock edge.
4.
Q stays 1 until the next rising edge loads D, or until a clear.

Common mistakes

Waiting for a clock edge. An asynchronous input acts immediately.
Holding an active-low preset at 0 during normal operation. That keeps Q stuck at 1; the idle level is 1.
Asserting preset and clear together. The result is invalid.

Practice Asynchronous preset

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Learn it step by step

Asynchronous preset is taught in Latches and Flip-Flops, Registers and Counters.

Latches and Flip-Flops →Registers →Counters →

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