Register overhead

Also called: sequencing overhead, pipeline overhead, pipeline register overhead

The part of each clock period used by the registers rather than the logic: tcq + tsu. Every pipeline stage pays it.

Every clock period has to cover more than just the logic. The registers themselves eat some of it: the launching flip-flop's clock to q delay tcq at the start, and the capturing flip-flop's setup time tsu at the end. Together, tcq + tsu is the register overhead (also called sequencing overhead).

T = tpd(logic) + tcq + tsu

This matters most in pipelining. Splitting logic into N stages divides the logic delay, but each stage still pays the full overhead:

the clock period can never drop below tcq + tsu, however thin the stages;
the latency grows by one overhead for each extra stage;
as stages get thinner, overhead becomes a bigger share of each period, so each extra stage helps less.

That's why real pipelines stop at a moderate number of stages: past a point, the registers cost more than the logic they split.

Worked example

Example

Diminishing returns

Logic with tpd = 12 ns is pipelined with registers whose tcq + tsu = 1 ns. Compare 1, 2, 4 and 12 equal stages.

1.
1 stage: T = 12 + 1 = 13 ns (about 77 MHz).
2.
2 stages: T = 6 + 1 = 7 ns (about 143 MHz).
3.
4 stages: T = 3 + 1 = 4 ns (250 MHz).
4.
12 stages: T = 1 + 1 = 2 ns (500 MHz). Half of every period is now overhead.
5.
No number of stages can get the period down to 1 ns, so f stays below 1 GHz.

Common mistakes

Paying the overhead once for the whole pipeline. Each stage pays it.
Thinking enough stages can make the clock arbitrarily fast. The overhead sets a floor on the period.

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Pipeline registers have tcq + tsu = 50 ps. However finely you split the logic, what is the upper limit on the clock frequency, in GHz?

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