Clock-to-Q delay

Also called: clock-to-Q, clock to Q, tcq, t_cq, tpcq

The longest time after a flip-flop's active clock edge until Q shows its new value. Written tcq; it is the flip-flop's propagation delay.

When the clock edge arrives, a d flip flop doesn't update Q instantly. The clock-to-Q delay tcq is the longest time after the edge before Q is guaranteed to show the newly captured value. It plays the same role for a flip-flop that the propagation delay plays for a gate.

Its partner is the minimum clock to q delay tcq(min), the earliest Q could start to change. Between tcq(min) and tcq, Q is uncertain.

Why it matters: in every register-to-register path, data can't even start through the logic until it has left the launching flip-flop. So tcq is the first term of the setup constraint:

T ≥ tcq + tpd + tsu

Forgetting it is a common slip that makes a design look faster than it is. Some textbooks write tpcq for this number.

Note how tcq differs from the two input rules, setup time and hold time. Those say when D must be steady; tcq says when Q becomes valid. All four numbers are measured from the active clock edge.

Worked example

Example

When is Q ready?

A flip-flop has tcq = 120 ps. Its clock rises at t = 2 ns. In the diagram above, each slot is one time step and Q lags the edge by one slot.

1.
Convert: 2 ns = 2000 ps.
2.
Q is guaranteed new at 2000 + 120 = 2120 ps = 2.12 ns.
3.
Any logic fed by Q starts working on the new value only from then.
4.
In the diagram, the edge at slot 3 captures D = 1, but Q only rises in slot 4. The edge at slot 7 captures D = 0, and Q falls in slot 8.

Common mistakes

Leaving tcq out of the setup check. Data can't enter the logic until it has left the flip-flop.
Confusing tcq with setup time. Setup is a rule about D before the edge; tcq is a delay on Q after it.
Using tcq in the hold check. Hold needs the earliest change, tcq(min).

Practice Clock-to-Q delay

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Timing and Sequential Logic lesson full course

What does a flip-flop's clock-to-Q delay tcq measure?

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Learn it step by step

Clock-to-Q delay is taught in Timing and Sequential Logic and Latches and Flip-Flops.

Timing and Sequential Logic →Latches and Flip-Flops →

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