Setup time

Also called: set-up time, t_setup, tsetup, setup window

The minimum time a flip-flop's data input must be stable before the active clock edge for the new value to be captured reliably.

The setup time (tsu) is how long before a clock edge a flip flop's data input must already be steady.

Why it exists: a flip-flop is not an ideal camera. Inside, it takes a little time for the new value to settle into its internal feedback loop. If D is still changing just before the edge, the flip-flop may capture the old value, the new value, or neither cleanly.

Setup time pairs with hold time, the time D must stay steady after the edge. Together they form a small window around each edge:

from (edge − tsu) to (edge + th), D must not change.

If D changes inside that window, the flip-flop may capture the wrong value or enter metastability, hovering between 0 and 1 before settling unpredictably.

What it means for design: the logic feeding D must finish its work at least tsu before the next edge. That sets the fastest safe clock. The setup constraint in the timing topic turns this into a formula for the minimum clock period.

Typical values are tens to hundreds of picoseconds inside a chip, and a few nanoseconds for discrete logic parts.

Worked examples

Example

Latest moment D may change

A flip-flop has tsu = 2 ns. A clock edge arrives at t = 50 ns. By when must D be stable?

1.
D must be stable from tsu before the edge.
2.
50 − 2 = 48 ns.
3.
So D may change up to t = 48 ns, and must then stay put through the edge.
4.
If the logic driving D settles at 48.5 ns, the setup time is violated by 0.5 ns.

Example

Checking a combined window

tsu = 1.5 ns, th = 0.5 ns, edge at t = 20 ns. D changes at t = 19 ns. Is that safe?

1.
Forbidden window: 20 − 1.5 = 18.5 ns to 20 + 0.5 = 20.5 ns.
2.
19 ns lies inside it.
3.
Not safe: it is a setup violation, because the change comes before the edge but too close to it.

Common mistakes

Confusing setup with hold. Setup is before the edge; hold is after it.
Thinking setup time is how long the flip-flop takes to change Q. That is the clock-to-Q delay.
Assuming a violation always captures the old value. The result can be wrong or metastable.

Practice Setup time

Interactive questions with instant feedback and a worked solution for every wrong answer.

Latches and Flip-Flops lesson full course

Counters lesson full course

A synchronous counter's flip-flops have tpd = 8 ns and a setup time of 4 ns. The slowest path through its T logic takes 6 ns. What is the shortest clock period it can use, in ns?

Timing and Sequential Logic lesson full course

Practice exams

Learn it step by step

Setup time is taught in Latches and Flip-Flops and Timing and Sequential Logic.

Latches and Flip-Flops →Timing and Sequential Logic →

All terms