Register transfer notation (RTN) describes hardware in terms of what registers do at each clock edge. Each statement is a register transfer, or micro-operation.
The pieces:
- R1 ← R2: at the next edge, R1 loads a copy of R2. R2 is unchanged.
- R1 ← R1 + R2: R1 loads the sum. An adder sits in front of R1's inputs.
- T1: R2 ← R1: a conditional transfer. It happens only at an edge where control signal T1 = 1. In hardware, T1 drives R2's load enable.
- A comma means both transfers happen at the same edge: T2: R1 ← R2, R2 ← R1.
- M[MAR] means the memory word at the address held in MAR.
The golden rule: everything on the right of an arrow is read from the values before the edge. All destinations update together afterwards. That is why R1 ← R2, R2 ← R1 at one edge performs a swap.
Why it matters: a processor's datapath is registers joined by combinational logic, and each instruction is a short sequence of transfers. The fetch of a simple CPU reads: MAR ← PC; then MDR ← M[MAR], PC ← PC + 1; then IR ← MDR. Reading RTN tells you exactly which load enables and MUX selects the control unit must set at each edge.
A register can only load one value per edge, so two transfers into the same register at one edge are impossible.