Register-to-register path

Also called: reg-to-reg path, flop-to-flop path, launching flip-flop, capturing flip-flop

A timing path that starts at one flip-flop, passes through combinational logic, and ends at another flip-flop on the same clock.

Almost every timing question in a synchronous circuit is about the same small pattern:

a launching flip-flop, whose Q changes at a clock edge;
some combinational logic;
a capturing flip-flop, whose D is fed by that logic.

Both flip-flops share the clock. A design has thousands of these paths, and each one gets two checks:

Setup: is the slowest data early enough for the next edge? T ≥ tcq + tpd + tsu.
Hold: is the fastest new data late enough to miss the same edge's hold window? tcq(min) + tcd ≥ th.

A path can fail either check, both, or neither. If the clock reaches the two flip-flops at different times, the difference is clock skew and both checks shift.

The same flip-flop is often the capturing end of one path and the launching end of the next. In a pipeline, each stage is one register-to-register path.

Worked example

Example

Both checks on one path

A path has tcq = 0.4 ns, tcq(min) = 0.1 ns, logic tpd = 3.0 ns, logic tcd = 0.2 ns, tsu = 0.3 ns and th = 0.25 ns. The clock is 250 MHz.

1.
Period: T = 1000 ÷ 250 = 4 ns.
2.
Setup: 0.4 + 3.0 + 0.3 = 3.7 ns ≤ 4 ns. Passes with 0.3 ns of slack.
3.
Hold: 0.1 + 0.2 = 0.3 ns ≥ 0.25 ns. Passes with 0.05 ns of slack.
4.
So the path works at 250 MHz.

Common mistakes

Thinking the capturing flip-flop captures the data at the same edge that launched it. It captures it at the next edge.
Running only the setup check. Hold must be checked on every path too.

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