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Conditional transfer

Also called: conditional register transfer, controlled transfer, guarded transfer

A register transfer that happens only at edges where a control signal is 1, written T1: R2 ← R1. The control signal drives the destination's load enable.

A conditional transfer is a register transfer with a condition in front:

T1: R2 ← R1

It means: at an edge where T1 = 1, R2 loads R1. At an edge where T1 = 0, R2 holds.

How it is built: R1's outputs are wired to R2's data inputs, and T1 drives R2's load enable. That's all.

When a register has several possible sources, a multiplexer picks the source and the load enable is the OR of the conditions. For

T1: R1 ← R2 and T2: R1 ← R3

R1's data inputs come from a 2:1 MUX choosing R2 or R3, and R1's load enable is . This only works if T1 and T2 are never 1 together; a register cannot load two values at once.

Several conditional transfers can share one control signal: T2: R1 ← R2, R2 ← R1 is a one-edge register swap that happens only when T2 = 1.

Why it matters: a CPU's control unit works by raising control signals like T1 at the right clock edges. Each control signal is, underneath, a load enable or a MUX select.

Worked examples

Example

Conditional transfers over three edges

4-bit registers start at R1 = 0001 (1) and R2 = 0011 (3). The design has T1: R1 ← R1 + R2 and T2: R2 ← R1.

  1. 1.

    Edge 1: T1 = 1, T2 = 0. R1 = 1 + 3 = 4 = 0100. R2 holds 0011.

  2. 2.

    Edge 2: T1 = 1, T2 = 1. Both use old values: R1 = 4 + 3 = 7 = 0111, R2 = old R1 = 0100.

  3. 3.

    Edge 3: T1 = 0, T2 = 0. Both hold: R1 = 0111, R2 = 0100.

Example

Two sources into one register

R4 has T5: R4 ← R2 and T6: R4 ← R3 + R2, and T5 and T6 are never 1 together. How is R4's input built?

  1. 1.

    A 2:1 MUX feeds R4's data inputs: the adder output (R3 + R2) when T6 = 1, R2 otherwise (select = T6).

  2. 2.

    R4's load enable is , so it loads when either transfer is requested.

  3. 3.

    When both are 0, R4 holds.

Common mistakes

  • Gating the clock with the condition instead of using it as a load enable.

  • Allowing two transfers into the same register at one edge.

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Conditional transfer is taught in Registers and Basic CPU / Computer Architecture.

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