A synchronous clear resets a register to 0, but only at the next clock edge. It is ordinary logic in front of each flip-flop's D input that makes the next value 0.
For a register that loads data N at every edge, with clear input C:
D =
With C = 0, D = N and the register loads normally. With C = 1, D = 0, so at the next edge every bit loads 0.
With a load enable as well, clear normally has priority, so C goes on the outside:
D =
Why priority: clear is how you recover a known state. If load could override it, a stuck or noisy load signal could stop the reset from working.
Compared with an asynchronous clear:
- A synchronous clear obeys the same edge rule as every other input, so it causes no timing surprises. Many FPGA and chip designers prefer it.
- But it needs a running clock, and a pulse that starts and ends between two edges is missed completely.
A synchronous clear is just one more candidate for the D-input logic to choose, alongside keep and new. The same trick gives a synchronous set (force a 1) by ORing instead of ANDing.
| D | ||||
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 |