A synchronous set is the mirror image of a synchronous clear: logic in front of a flip-flop's D input that makes the next value 1. Nothing happens until the next rising edge.
Where a clear ANDs onto the D logic to force a 0, a set ORs S onto it to force a 1. For a bit with load L, data N and set S, with set having priority:
D =
- S = 1: D = 1 whatever the rest are, so the bit sets at the edge.
- S = 0: the usual load-enable MUX, D = .
The asynchronous version is the asynchronous preset, which forces Q = 1 immediately without waiting for an edge.
Where it is used: registers that must start at a nonzero value, such as a ring counter that starts at 1000, or flags that a state machine must raise in step with the clock.
If a register has both a synchronous set and a synchronous clear, the designer must choose which wins when both are 1 and nest them in that order.
| D | ||||
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |