Clock skew

Also called: skew, tskew, t_skew, positive skew, negative skew, clock distribution

The difference in arrival time of the same clock edge at two flip-flops. Here: capture time minus launch time.

The clock reaches each flip-flop through real wires and buffers, so the same edge arrives at different flip-flops at slightly different times. That difference is clock skew.

This course uses one sign convention:

tskew = (when the edge reaches the capturing flip-flop) − (when it reaches the launching flip-flop)

Positive skew means the capturing flip-flop's clock is late. Some books use the opposite sign, so check which one a question uses.

Skew shifts both timing checks, in opposite directions:

Setup: a late capturing edge gives slow data more time. T ≥ tcq + tpd + tsu − tskew.
Hold: a late capturing edge also keeps its hold window open longer, so fast data is more likely to break in. tcq(min) + tcd ≥ th + tskew.

So positive skew helps setup and hurts hold; negative skew does the reverse. Chip designers build balanced clock trees to keep skew small, and a gated clock is a classic way to create skew by accident.

Worked examples

Example

Negative skew in both checks

The clock reaches the launching flip-flop at 50 ps and the capturing flip-flop at 20 ps. tcq = 90 ps, tcq(min) = 30 ps, logic tpd = 500 ps, logic tcd = 20 ps, tsu = 40 ps, th = 25 ps.

1.
Skew = capture − launch = 20 − 50 = −30 ps. The capturing edge is early.
2.
Setup: Tmin = 90 + 500 + 40 − (−30) = 660 ps. Without skew it would be 630 ps, so negative skew hurt setup.
3.
Hold: arrival 30 + 20 = 50 ps; requirement th + tskew = 25 + (−30) = −5 ps. Hold slack = 50 − (−5) = +55 ps. Negative skew helped hold.

Example

Reading skew off a diagram

In the diagram above, each slot is 50 ps. The launching clock rises at slot 3 and the capturing clock at slot 4.

1.
Capture − launch = one slot = +50 ps.
2.
Positive skew: setup gains 50 ps of room, and hold needs 50 ps more.

Common mistakes

Flipping the sign. Always compute capture minus launch and keep the sign through the formulas.
Thinking skew only affects setup. The same skew shifts hold the other way.
Adding skew to Tmin when it's positive. Positive skew is subtracted in the setup check.

Practice Clock skew

Interactive questions with instant feedback and a worked solution for every wrong answer.

Timing and Sequential Logic lesson full course

Practice exams

Learn it step by step

Clock skew is taught in Timing and Sequential Logic.

Timing and Sequential Logic →

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