Gated clock

Also called: clock gating, gating the clock

A clock passed through logic, such as an AND with an enable, before reaching a flip-flop. Risky: it can create glitches and clock skew.

A gated clock is what you get when you feed a flip-flop's clock pin from logic, for example G = CLK · EN, so that the register only sees edges while EN = 1. It looks like a neat way to make a register hold, but it breaks the rules of synchronous design:

Glitches become clock edges. EN comes from logic, which can glitch, and its timing isn't tied to the clock. If EN changes while CLK is high, G gets an extra edge at the wrong time or a pulse too short to trust.
Skew. The AND gate delays G, so the gated register is clocked later than the rest. That's clock skew, which can cause hold violations.
Analysis gets harder. The clock is now a data-dependent signal.

The safe alternative is a clock enable: keep the clock clean and put a 2-to-1 multiplexer in front of D, so D = new data when EN = 1 and D = Q (reload the old value) when EN = 0.

Real chips do gate clocks to save power, but with special glitch-free clock-gating cells and careful timing, not ordinary logic.

Worked example

Example

A wrongly timed edge

In the diagram, EN changes while CLK is high: it rises in slot 4 and falls in slot 8.

1.
The real clock rises in slots 3, 7 and 11.
2.
G rises in slot 4, a slot after the real edge, because EN only arrives then. The gated register is clocked at the wrong time.
3.
G's pulse in slot 7 lasts only one slot, cut short when EN falls in slot 8. Short pulses like this may not clock a flip-flop reliably.
4.
With a clock enable instead, the register would see every real edge and simply reload Q when EN = 0.

Common mistakes

Thinking a gated clock is just an enable. It changes when edges happen, not only whether data loads.
Ignoring the AND gate's delay. It skews that register's clock against the others.

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Timing and Sequential Logic: Exam 4 · 1 question

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