Synchronous design is the set of habits that makes digital hardware predictable. Follow them and every path needs only two checks, setup and hold.
The rules:
- One clock. Every flip-flop is driven by the same, clean clock.
- State lives in flip-flops. No loops of combinational logic that feed back on themselves.
- Logic sits between registers. Every path starts and ends at a flip-flop (a register to register path).
- Never gate the clock with logic. To make a register sometimes hold, use a clock enable in front of D, not a gated clock.
- Synchronize asynchronous inputs with a two flip flop synchronizer before using them.
The payoff: a flip-flop only looks at D in a small window around each edge. Glitches in the logic between registers die out long before that window, as long as the setup constraint holds. So designers can ignore glitches almost everywhere.
Glitches still matter wherever something reacts at once: clock pins, asynchronous clear and preset inputs, and outputs that leave the chip.