Flip-flop timing parameters

Also called: flip-flop timing, sequential timing parameters

The four numbers that say when a flip-flop can be trusted, all measured from the clock edge: tsu, th, tcq(min) and tcq.

Every edge-triggered flip-flop comes with four timing numbers, all measured from its active clock edge. Two are requirements on the D input; two are delays on the Q output.

Setup time tsu: D must be stable at least this long before the edge.
Hold time th: D must stay stable at least this long after the edge.
Minimum clock-to-Q tcq(min): Q can't start to change until this long after the edge.
Clock-to-Q tcq: Q is guaranteed new by this long after the edge.

The first two define the setup and hold window around the edge. The second two are the flip-flop's contamination and propagation delays.

They feed the two checks on every register-to-register path:

Setup uses the slow numbers: T ≥ tcq + tpd + tsu.
Hold uses the fast numbers: tcq(min) + tcd ≥ th.

Worked example

Example

Ordering events around one edge

A flip-flop has tsu = 120 ps, th = 40 ps, tcq(min) = 60 ps and tcq = 110 ps. The clock rises at t = 1000 ps. Put the moments in order.

1.
D must be stable from 1000 − 120 = 880 ps.
2.
The clock edge: 1000 ps.
3.
D may change again after 1000 + 40 = 1040 ps.
4.
Q may start to change at 1000 + 60 = 1060 ps.
5.
Q is certainly new at 1000 + 110 = 1110 ps.
6.
Order: 880, 1000, 1040, 1060, 1110 ps.

Common mistakes

Measuring setup time after the edge. Setup is before, hold is after.
Treating tsu and th as delays. They're rules the input must obey; the delays are on Q.
Mixing the slow and fast numbers between the setup and hold checks.

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Timing and Sequential Logic lesson full course

What does a flip-flop's clock-to-Q delay tcq measure?

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Flip-flop timing parameters is taught in Timing and Sequential Logic and Latches and Flip-Flops.

Timing and Sequential Logic →Latches and Flip-Flops →

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