Maximum clock frequency (fmax)

Also called: maximum frequency, f_max, max clock frequency, maximum operating frequency

The fastest clock a synchronous circuit can use: 1 ÷ Tmin, where Tmin = tcq + tpd + tsu on the slowest register-to-register path.

Every synchronous circuit has a speed limit. The maximum clock frequency fmax is the highest clock rate at which every register-to-register path still meets the setup constraint.

To find it:

For each path, compute tcq + tpd + tsu, using the path's critical tpd.
Take the largest of these. That's the minimum clock period Tmin.
fmax = 1 / Tmin.

Unit shortcuts make step 3 quick: fmax in MHz = 1000 ÷ Tmin in ns, and fmax in GHz = 1 ÷ Tmin in ns.

What raises fmax:

Faster logic on the critical path. Speeding up other paths does nothing.
Pipelining: cutting the logic into shorter stages.
Positive clock skew on the critical path, which subtracts from Tmin.

What doesn't: anything about hold. The hold constraint has no clock period in it, so it neither limits nor is fixed by the clock speed.

Worked example

Example

fmax from three paths

All flip-flops have tcq = 0.5 ns and tsu = 0.3 ns. Three register-to-register paths have logic delays of 3.2, 4.2 and 2.0 ns.

1.
Path 1: 0.5 + 3.2 + 0.3 = 4.0 ns.
2.
Path 2: 0.5 + 4.2 + 0.3 = 5.0 ns.
3.
Path 3: 0.5 + 2.0 + 0.3 = 2.8 ns.
4.
The largest is 5.0 ns, so Tmin = 5 ns and fmax = 1000 ÷ 5 = 200 MHz.
5.
Shortening paths 1 or 3 wouldn't help; only path 2 sets the clock.

Common mistakes

Using the average or the fastest path. The slowest path sets fmax.
Forgetting tcq and tsu, which gives a frequency that's too high.
Losing the unit prefix: 1 ÷ 5 ns is 0.2 GHz, not 0.2 Hz.

Practice Maximum clock frequency (fmax)

Interactive questions with instant feedback and a worked solution for every wrong answer.

Counters lesson full course

Timing and Sequential Logic lesson full course

And 3 more in the Timing and Sequential Logic lesson.

Practice exams

Learn it step by step

Maximum clock frequency (fmax) is taught in Timing and Sequential Logic.

Timing and Sequential Logic →

All terms