Minimum clock period (Tmin)

Also called: minimum period, T_min, min clock period

The shortest clock period that still meets setup on every path: Tmin = tcq + tpd + tsu for the slowest register-to-register path.

The minimum clock period Tmin is the shortest a clock cycle can be while every register-to-register path still meets the setup constraint. On one path it's:

Tmin = tcq + tpd + tsu

Read it as a timeline after a clock edge: the launching flip-flop's Q is ready after the clock to q delay tcq, the logic needs its critical path delay tpd, and the result must then sit still for the setup time tsu before the next edge.

For a whole circuit, Tmin is the largest value over all paths, and the maximum clock frequency is 1 / Tmin.

Any clock period equal to or longer than Tmin works for setup. A shorter one causes a setup violation on at least one path. With clock skew, subtract the skew: Tmin = tcq + tpd + tsu − tskew.

Worked example

Example

Tmin from a timeline

A path has tcq = 150 ps, logic tpd = 1.1 ns and tsu = 90 ps. The clock edge is at t = 0.

1.
Q is valid at 150 ps.
2.
The logic output is valid at 150 + 1100 = 1250 ps.
3.
It must be stable 90 ps before the next edge, so the next edge can come at 1250 + 90 = 1340 ps at the earliest.
4.
Tmin = 1340 ps = 1.34 ns, so fmax = 1000 ÷ 1.34 ≈ 746 MHz.

Common mistakes

Using the logic delay alone as Tmin.
Taking the smallest path total. The slowest path sets the minimum period.
Adding hold time. Hold is a separate check and never sets the period.

Practice Minimum clock period (Tmin)

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Timing and Sequential Logic lesson full course

A register-to-register path has tcq = 1 ns, logic tpd = 6 ns and tsu = 1 ns. What is the minimum clock period, in ns?

Learn it step by step

Minimum clock period (Tmin) is taught in Timing and Sequential Logic.

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