Full state decoding uses every bit of the counter. But a mod n counter never visits some codes, and those unused states act like don't-cares for the decoder. So you can often leave bits out.
The test is simple: the reduced decoder must be 1 in the target state and 0 in every other state the counter really visits. Codes it never reaches don't count.
- In a BCD counter (0 to 9), only 8 and 9 have Q3 = 1, and only 9 also has Q0 = 1. So state 9 is detected by instead of .
- In a mod-12 counter with an asynchronous clear that detects 12 =
1100, the states reached are 0 to 12. Only 12 has Q3 = Q2 = 1, so a 2-input NAND does the job.
It's exactly K-map simplification with don't-cares: the unused codes let you make a bigger group. Partial decoding saves gate inputs, which is why it's common in mod-N clear logic.
| Q3Q2\Q1Q0 | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 0m0 | 0m1 | 0m3 | 0m2 |
| 01 | 0m4 | 0m5 | 0m7 | 0m6 |
| 11 | Xm12 | Xm13 | Xm15 | Xm14 |
| 10 | 0m8 | 1m9 | Xm11 | Xm10 |