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Setup violation

Also called: setup failure, setup time violation, negative setup slack

A timing failure where data reaches a flip-flop too late, less than tsu before the clock edge, so the wrong value may be captured.

A setup violation happens when a path fails the setup constraint: tcq + tpd + tsu is longer than the clock period, so the setup slack is negative. The new data hasn't settled at the capturing flip-flop's D by tsu before the edge.

What goes wrong: the flip-flop may capture the old value, some bits may be old and some new, or it may go metastable if D is changing inside its window. Any of these breaks the circuit's logic.

The good news is that setup violations are always fixable:

  • Slow the clock. A longer period gives the data more time. This always works.
  • Speed up the critical path: faster gates, fewer logic levels, or a better structure (for example carry-lookahead instead of ripple-carry).
  • Pipeline the logic, so each stage has less to do.
  • Use positive clock skew on that path, carefully, since it hurts hold.

Compare a hold violation, which the clock speed can't fix at all.

Worked example

Example

Spotting and fixing one

A design runs at 1 GHz. One path has tcq = 100 ps, logic tpd = 850 ps and tsu = 80 ps.

  1. 1.

    Period: T = 1 ÷ 1 GHz = 1 ns = 1000 ps.

  2. 2.

    Needed: 100 + 850 + 80 = 1030 ps.

  3. 3.

    Slack = 1000 − 1030 = −30 ps: a setup violation.

  4. 4.

    Fix 1: slow the clock to at most 1 ÷ 1030 ps ≈ 971 MHz.

  5. 5.

    Fix 2: keep 1 GHz and cut the logic to tpd ≤ 1000 − 100 − 80 = 820 ps.

Common mistakes

  • Trying to fix a setup violation by adding delay. That's the hold fix, and it makes setup worse.

  • Thinking only a faster chip helps. Slowing the clock always removes a setup violation.

Practice Setup violation

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Learn it step by step

Setup violation is taught in Timing and Sequential Logic.

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