To hold is to keep the stored value exactly as it is: Q⁺ = Q. It is the condition that makes a storage element a memory at all.
How each element is told to hold:
- NOR SR latch: S = R = 0.
- NAND SR latch: = = 1.
- Gated D latch: enable inactive (EN = 0).
- JK flip-flop: J = K = 0 at the edge.
- T flip-flop: T = 0 at the edge.
- D flip-flop: between edges it always holds; at an edge it holds only if D happens to equal Q.
- register with load enable: L = 0, so the MUX feeds Q back into D.
- universal shift register: mode
00.
The key point for tracing: hold depends on the present value. The output in a hold slot equals the output just before it, so to predict Q you look back to the last set, reset, load or toggle.
Don't confuse hold with hold time. Hold time is a timing requirement: how long D must stay steady after a clock edge. Hold, here, is an input combination that means "keep Q".
And don't confuse hold with clear. Holding a 1 keeps a 1; it does not reset anything.