Maximum counting frequency

Also called: maximum counter frequency, counter fmax, maximum clock frequency of a counter

The fastest clock a counter can take and still settle correctly between edges: 1 / (n × tpd) for a ripple counter, 1 / (tpd + logic + setup) for a synchronous one.

Every counter needs some time after each edge before it's ready for the next. The maximum counting frequency is 1 divided by the shortest safe clock period.

Ripple counter. In the worst case the change ripples through all n stages, so the count settles n × tpd after the edge. The period must cover that, plus the delay of any logic that reads the count:

f_max = 1 / (n × tpd)

It gets slower as you add bits.

Synchronous counter. After an edge, three things happen in series:

the flip-flop outputs change (tpd);
the new values pass through the AND / XOR next-state logic;
the results reach the flip-flop inputs at least a setup time before the next edge.

f_max = 1 / (tpd + logic delay + setup time)

This doesn't multiply by n, so wide synchronous counters stay fast. It's the same setup constraint that governs any register-to-register path.

Worked examples

Example

Ripple vs synchronous, 8 bits

Flip-flops have tpd = 10 ns and setup time 5 ns. The synchronous counter's next-state logic takes 5 ns.

1.
8-bit ripple: period ≥ 8 × 10 = 80 ns, so f_max = 1 / 80 ns = 12.5 MHz.
2.
8-bit synchronous: period ≥ 10 + 5 + 5 = 20 ns, so f_max = 1 / 20 ns = 50 MHz.
3.
Widen both to 16 bits: ripple drops to 1 / 160 ns = 6.25 MHz; synchronous stays at about 50 MHz.

Example

How much logic fits?

A synchronous counter must run at 100 MHz with tpd = 3 ns and setup time 2 ns. How long can the next-state logic take?

1.
Period = 1 / 100 MHz = 10 ns.
2.
Logic budget = 10 − 3 − 2 = 5 ns.

Common mistakes

Forgetting the setup time in the synchronous formula.
Multiplying by n for a synchronous counter. Only a ripple counter's delay grows with its width.
Mixing units: 1 / 20 ns = 50 MHz, not 50 kHz.

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